Mercurial > vec
annotate src/cpu.c @ 27:d00b95f95dd1 default tip
impl/arm/neon: it compiles again, but is untested
author | Paper <paper@tflc.us> |
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date | Mon, 25 Nov 2024 00:33:02 -0500 |
parents | 92156fe32755 |
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rev | line source |
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1 /** |
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2 * vec - a tiny SIMD vector library in C99 |
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3 * |
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4 * Copyright (c) 2024 Paper |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in all |
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14 * copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
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19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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22 * SOFTWARE. |
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23 **/ |
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24 |
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25 /* Detect CPU SIMD support. Much of this code was stolen from SDL. |
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26 * |
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27 * Simple DirectMedia Layer |
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28 * Copyright (C) 1997-2024 Sam Lantinga <slouken@libsdl.org> |
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29 * |
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30 * This software is provided 'as-is', without any express or implied |
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31 * warranty. In no event will the authors be held liable for any damages |
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32 * arising from the use of this software. |
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33 * |
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34 * Permission is granted to anyone to use this software for any purpose, |
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35 * including commercial applications, and to alter it and redistribute it |
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36 * freely, subject to the following restrictions: |
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37 * |
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38 * 1. The origin of this software must not be misrepresented; you must not |
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39 * claim that you wrote the original software. If you use this software |
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40 * in a product, an acknowledgment in the product documentation would be |
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41 * appreciated but is not required. |
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42 * 2. Altered source versions must be plainly marked as such, and must not be |
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43 * misrepresented as being the original software. |
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44 * 3. This notice may not be removed or altered from any source distribution. |
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45 */ |
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46 |
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47 #include "vec/vec.h" |
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48 #include "vec/cpu.h" |
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49 |
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50 #if defined(__MACOSX__) && (defined(__ppc__) || defined(__ppc64__)) |
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51 # include <sys/sysctl.h> // For AltiVec check |
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52 #elif defined(__OpenBSD__) && defined(__powerpc__) |
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53 # include <sys/types.h> |
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54 # include <sys/sysctl.h> // For AltiVec check |
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55 # include <machine/cpu.h> |
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56 #elif defined(__FreeBSD__) && defined(__powerpc__) |
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57 # include <machine/cpu.h> |
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58 # include <sys/auxv.h> |
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59 #elif defined(VEC_COMPILER_HAS_ALTIVEC) |
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60 # include <signal.h> |
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61 # include <setjmp.h> |
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62 #endif |
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63 |
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64 #ifdef __FreeBSD__ |
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65 # include <sys/param.h> |
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66 #endif |
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67 |
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68 #if (defined(__linux__) || defined(__ANDROID__)) && defined(__arm__) |
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69 # include <unistd.h> |
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70 # include <sys/types.h> |
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71 # include <sys/stat.h> |
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72 # include <fcntl.h> |
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73 # include <elf.h> |
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74 |
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75 /*#include <asm/hwcap.h>*/ |
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76 # ifndef AT_HWCAP |
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77 # define AT_HWCAP 16 |
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78 # endif |
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79 # ifndef AT_PLATFORM |
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80 # define AT_PLATFORM 15 |
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81 # endif |
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82 # ifndef HWCAP_NEON |
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83 # define HWCAP_NEON (1 << 12) |
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84 # endif |
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85 #endif |
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86 |
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87 static inline int vec_CPU_have_CPUID(void) |
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88 { |
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89 int has_CPUID = 0; |
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90 |
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91 #if (defined(__GNUC__) || defined(__llvm__)) && defined(__i386__) |
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92 __asm__ ( |
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93 " pushfl # Get original EFLAGS \n" |
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94 " popl %%eax \n" |
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95 " movl %%eax,%%ecx \n" |
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96 " xorl $0x200000,%%eax # Flip ID bit in EFLAGS \n" |
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97 " pushl %%eax # Save new EFLAGS value on stack \n" |
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98 " popfl # Replace current EFLAGS value \n" |
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99 " pushfl # Get new EFLAGS \n" |
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100 " popl %%eax # Store new EFLAGS in EAX \n" |
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101 " xorl %%ecx,%%eax # Can not toggle ID bit, \n" |
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102 " jz 1f # Processor=80486 \n" |
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103 " movl $1,%0 # We have CPUID support \n" |
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104 "1: \n" |
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105 : "=m" (has_CPUID) |
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106 : |
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107 : "%eax", "%ecx" |
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108 ); |
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109 #elif (defined(__GNUC__) || defined(__llvm__)) && defined(__x86_64__) |
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110 /* Technically, if this is being compiled under __x86_64__ then it has |
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111 CPUid by definition. But it's nice to be able to prove it. :) */ |
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112 __asm__ ( |
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113 " pushfq # Get original EFLAGS \n" |
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114 " popq %%rax \n" |
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115 " movq %%rax,%%rcx \n" |
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116 " xorl $0x200000,%%eax # Flip ID bit in EFLAGS \n" |
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117 " pushq %%rax # Save new EFLAGS value on stack \n" |
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118 " popfq # Replace current EFLAGS value \n" |
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119 " pushfq # Get new EFLAGS \n" |
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120 " popq %%rax # Store new EFLAGS in EAX \n" |
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121 " xorl %%ecx,%%eax # Can not toggle ID bit, \n" |
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122 " jz 1f # Processor=80486 \n" |
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123 " movl $1,%0 # We have CPUID support \n" |
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124 "1: \n" |
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125 : "=m" (has_CPUID) |
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126 : |
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127 : "%rax", "%rcx" |
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128 ); |
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129 #elif (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__) |
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130 __asm { |
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131 pushfd ; Get original EFLAGS |
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132 pop eax |
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133 mov ecx, eax |
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134 xor eax, 200000h ; Flip ID bit in EFLAGS |
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135 push eax ; Save new EFLAGS value on stack |
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136 popfd ; Replace current EFLAGS value |
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137 pushfd ; Get new EFLAGS |
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138 pop eax ; Store new EFLAGS in EAX |
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139 xor eax, ecx ; Can not toggle ID bit, |
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140 jz done ; Processor=80486 |
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141 mov has_CPUID,1 ; We have CPUID support |
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142 done: |
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143 } |
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144 #elif defined(_MSC_VER) && defined(_M_X64) |
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145 has_CPUID = 1; |
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146 #elif defined(__sun) && defined(__i386) |
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147 __asm ( |
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148 " pushfl \n" |
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149 " popl %eax \n" |
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150 " movl %eax,%ecx \n" |
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151 " xorl $0x200000,%eax \n" |
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152 " pushl %eax \n" |
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153 " popfl \n" |
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154 " pushfl \n" |
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155 " popl %eax \n" |
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156 " xorl %ecx,%eax \n" |
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157 " jz 1f \n" |
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158 " movl $1,-8(%ebp) \n" |
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159 "1: \n" |
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160 ); |
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161 #elif defined(__sun) && defined(__amd64) |
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162 __asm ( |
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163 " pushfq \n" |
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164 " popq %rax \n" |
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165 " movq %rax,%rcx \n" |
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166 " xorl $0x200000,%eax \n" |
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167 " pushq %rax \n" |
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168 " popfq \n" |
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169 " pushfq \n" |
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170 " popq %rax \n" |
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171 " xorl %ecx,%eax \n" |
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172 " jz 1f \n" |
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173 " movl $1,-8(%rbp) \n" |
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174 "1: \n" |
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175 ); |
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176 #endif |
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177 |
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178 return has_CPUID; |
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179 } |
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180 |
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181 #if (defined(__GNUC__) || defined(__llvm__)) && defined(__i386__) |
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182 # define VEC_CPU_CPUID(func, a, b, c, d) \ |
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183 __asm__ __volatile__( \ |
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184 " pushl %%ebx \n" \ |
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185 " xorl %%ecx,%%ecx \n" \ |
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186 " cpuid \n" \ |
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187 " movl %%ebx, %%esi \n" \ |
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188 " popl %%ebx \n" \ |
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189 : "=a"(a), "=S"(b), "=c"(c), "=d"(d) \ |
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190 : "a"(func)) |
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191 #elif (defined(__GNUC__) || defined(__llvm__)) && defined(__x86_64__) |
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192 # define VEC_CPU_CPUID(func, a, b, c, d) \ |
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193 __asm__ __volatile__( \ |
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194 " pushq %%rbx \n" \ |
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195 " xorq %%rcx,%%rcx \n" \ |
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196 " cpuid \n" \ |
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197 " movq %%rbx, %%rsi \n" \ |
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198 " popq %%rbx \n" \ |
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199 : "=a"(a), "=S"(b), "=c"(c), "=d"(d) \ |
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200 : "a"(func)) |
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201 #elif (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__) |
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202 # define VEC_CPU_CPUID(func, a, b, c, d) \ |
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203 __asm { \ |
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204 __asm mov eax, func \ |
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205 __asm xor ecx, ecx \ |
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206 __asm cpuid \ |
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207 __asm mov a, eax \ |
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208 __asm mov b, ebx \ |
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209 __asm mov c, ecx \ |
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210 __asm mov d, edx \ |
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211 } |
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212 #elif (defined(_MSC_VER) && defined(_M_X64)) |
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213 // Use __cpuidex instead of __cpuid because ICL does not clear ecx register |
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214 # define VEC_CPU_CPUID(func, a, b, c, d) \ |
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215 do { \ |
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Paper <paper@tflc.us>
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216 int CPUInfo[4]; \ |
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217 __cpuidex(CPUInfo, func, 0); \ |
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218 a = CPUInfo[0]; \ |
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219 b = CPUInfo[1]; \ |
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220 c = CPUInfo[2]; \ |
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221 d = CPUInfo[3]; \ |
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222 } while (0) |
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223 #else |
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224 # define VEC_CPU_CPUID(func, a, b, c, d) \ |
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225 do { \ |
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226 a = b = c = d = 0; \ |
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227 (void)a; \ |
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228 (void)b; \ |
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229 (void)c; \ |
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230 (void)d; \ |
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231 } while (0) |
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232 #endif |
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233 |
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234 // --------------------------------------------------------------- |
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235 |
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236 static int vec_CPU_CPUIDFeatures[4]; |
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237 static int vec_CPU_CPUIDMaxFunction = 0; |
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238 static int vec_CPU_OSSavesYMM = 0; |
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239 static int vec_CPU_OSSavesZMM = 0; |
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240 |
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241 static inline void vec_CPU_get_CPUID_features(void) |
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242 { |
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243 static int checked = 0; |
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244 if (!checked) { |
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245 checked = 1; |
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246 if (vec_CPU_have_CPUID()) { |
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247 int a, b, c, d; |
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248 VEC_CPU_CPUID(0, a, b, c, d); |
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249 vec_CPU_CPUIDMaxFunction = a; |
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250 if (vec_CPU_CPUIDMaxFunction >= 1) { |
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251 VEC_CPU_CPUID(1, a, b, c, d); |
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252 vec_CPU_CPUIDFeatures[0] = a; |
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253 vec_CPU_CPUIDFeatures[1] = b; |
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254 vec_CPU_CPUIDFeatures[2] = c; |
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255 vec_CPU_CPUIDFeatures[3] = d; |
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256 |
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257 // Check to make sure we can call xgetbv |
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258 if (c & 0x08000000) { |
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259 // Call xgetbv to see if YMM (etc) register state is saved |
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260 #if (defined(__GNUC__) || defined(__llvm__)) && (defined(__i386__) || defined(__x86_64__)) |
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261 __asm__(".byte 0x0f, 0x01, 0xd0" |
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262 : "=a"(a) |
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263 : "c"(0) |
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264 : "%edx"); |
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265 #elif defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_X64)) && (_MSC_FULL_VER >= 160040219) // VS2010 SP1 |
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266 a = (int)_xgetbv(0); |
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267 #elif (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__) |
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268 __asm { |
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269 xor ecx, ecx |
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270 _asm _emit 0x0f _asm _emit 0x01 _asm _emit 0xd0 |
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271 mov a, eax |
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272 } |
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273 #endif |
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274 vec_CPU_OSSavesYMM = ((a & 6) == 6) ? 1 : 0; |
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275 vec_CPU_OSSavesZMM = (vec_CPU_OSSavesYMM && ((a & 0xe0) == 0xe0)) ? 1 : 0; |
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276 } |
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277 } |
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278 } |
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279 } |
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280 } |
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281 |
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282 #if !((defined(__MACOSX__) && (defined(__ppc__) || defined(__ppc64__))) || (defined(__OpenBSD__) && defined(__powerpc__))) && defined(VEC_COMPILER_HAS_ALTIVEC) && defined(__GNUC__) |
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283 static jmp_buf vec_jmpbuf; |
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284 static void vec_CPU_illegal_instruction(int sig) |
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285 { |
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286 longjmp(vec_jmpbuf, 1); |
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287 } |
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288 #endif |
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289 |
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290 static int vec_CPU_have_ALTIVEC(void) |
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291 { |
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292 volatile int altivec = 0; |
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293 #if (defined(__MACOSX__) && (defined(__ppc__) || defined(__ppc64__))) || (defined(__OpenBSD__) && defined(__powerpc__)) |
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294 int selectors[2] = { |
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295 # ifdef __OpenBSD__ |
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296 CTL_MACHDEP, CPU_ALTIVEC |
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297 # else |
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298 CTL_HW, HW_VECTORUNIT |
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299 # endif |
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300 }; |
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301 int hasVectorUnit = 0; |
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302 vec_uintsize length = sizeof(hasVectorUnit); |
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303 int error = sysctl(selectors, 2, &hasVectorUnit, &length, NULL, 0); |
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304 if (!error) |
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305 altivec = (hasVectorUnit != 0); |
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306 #elif defined(__FreeBSD__) && defined(__powerpc__) |
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307 unsigned long cpufeatures = 0; |
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308 elf_aux_info(AT_HWCAP, &cpufeatures, sizeof(cpufeatures)); |
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309 altivec = cpufeatures & PPC_FEATURE_HAS_ALTIVEC; |
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310 #elif defined(VEC_COMPILER_HAS_ALTIVEC) && defined(__GNUC__) |
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311 void (*handler)(int sig); |
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312 handler = signal(SIGILL, vec_CPU_illegal_instruction); |
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313 if (!setjmp(vec_jmpbuf)) { |
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314 __asm__ __volatile__("mtspr 256, %0\n\t" |
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315 "vand %%v0, %%v0, %%v0" ::"r"(-1)); |
23
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316 altivec = 1; |
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317 } |
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318 signal(SIGILL, handler); |
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319 #endif |
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320 return altivec; |
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321 } |
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322 |
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323 static int vec_CPU_have_ALTIVEC_VSX(void) |
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324 { |
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325 volatile int vsx = 0; |
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326 #if defined(VEC_COMPILER_HAS_ALTIVEC_VSX) && defined(__GNUC__) |
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327 # warning Compiling UNTESTED code for VSX. |
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328 void (*handler)(int sig); |
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329 handler = signal(SIGILL, vec_CPU_illegal_instruction); |
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330 if (!setjmp(vec_jmpbuf)) { |
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331 // this is completely untested |
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332 //__asm__ __volatile__("mtspr 256, %0\n\t" |
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333 // "xxland %%v0, %%v0, %%v0" ::"r"(-1)); |
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334 //vsx = 1; |
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335 } |
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336 signal(SIGILL, handler); |
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337 #endif |
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338 return vsx; |
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339 } |
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340 |
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341 #define vec_CPU_have_MMX() (vec_CPU_CPUIDFeatures[3] & 0x00800000) |
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342 #define vec_CPU_have_SSE() (vec_CPU_CPUIDFeatures[3] & 0x02000000) |
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343 #define vec_CPU_have_SSE2() (vec_CPU_CPUIDFeatures[3] & 0x04000000) |
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344 #define vec_CPU_have_SSE3() (vec_CPU_CPUIDFeatures[2] & 0x00000001) |
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345 #define vec_CPU_have_SSE41() (vec_CPU_CPUIDFeatures[2] & 0x00080000) |
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346 #define vec_CPU_have_SSE42() (vec_CPU_CPUIDFeatures[2] & 0x00100000) |
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347 #define vec_CPU_have_AVX() (vec_CPU_OSSavesYMM && (vec_CPU_CPUIDFeatures[2] & 0x10000000)) |
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348 |
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349 static inline int vec_CPU_have_AVX2(void) |
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350 { |
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351 if (vec_CPU_OSSavesYMM && (vec_CPU_CPUIDMaxFunction >= 7)) { |
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352 int a, b, c, d; |
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353 VEC_CPU_CPUID(7, a, b, c, d); |
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354 return b & 0x00000020; |
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355 (void)a, (void)c, (void)d; |
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356 } |
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357 return 0; |
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358 } |
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359 |
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360 static inline int vec_CPU_have_AVX512F(void) |
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361 { |
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362 if (vec_CPU_OSSavesYMM && (vec_CPU_CPUIDMaxFunction >= 7)) { |
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363 int a, b, c, d; |
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364 VEC_CPU_CPUID(7, a, b, c, d); |
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365 return b & 0x00000020; |
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366 (void)a, (void)c, (void)d; |
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367 } |
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368 return 0; |
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369 } |
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370 |
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371 #if defined(__linux__) && defined(__arm__) && !defined(HAVE_GETAUXVAL) |
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372 static int readProcAuxvForNeon(void) |
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373 { |
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374 int neon = 0; |
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375 int fd; |
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376 |
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377 fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC); |
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378 if (fd >= 0) { |
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379 Elf32_auxv_t aux; |
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380 while (read(fd, &aux, sizeof(aux)) == sizeof(aux)) { |
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381 if (aux.a_type == AT_HWCAP) { |
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382 neon = (aux.a_un.a_val & HWCAP_NEON) == HWCAP_NEON; |
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383 break; |
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384 } |
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385 } |
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386 close(fd); |
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Paper <paper@tflc.us>
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diff
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|
387 } |
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388 return neon; |
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Paper <paper@tflc.us>
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389 } |
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Paper <paper@tflc.us>
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|
390 #endif |
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Paper <paper@tflc.us>
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|
391 |
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Paper <paper@tflc.us>
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392 static int vec_CPU_have_NEON(void) |
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Paper <paper@tflc.us>
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|
393 { |
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Paper <paper@tflc.us>
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394 /* The way you detect NEON is a privileged instruction on ARM, so you have |
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395 query the OS kernel in a platform-specific way. :/ */ |
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Paper <paper@tflc.us>
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396 #if defined(SDL_CPUINFO_DISABLED) |
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397 return 0; /* disabled */ |
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398 #elif (defined(__WINDOWS__) || defined(__WINRT__) || defined(__GDK__)) && (defined(_M_ARM) || defined(_M_ARM64)) |
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399 /* Visual Studio, for ARM, doesn't define __ARM_ARCH. Handle this first. */ |
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400 /* Seems to have been removed */ |
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401 #ifndef PF_ARM_NEON_INSTRUCTIONS_AVAILABLE |
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402 #define PF_ARM_NEON_INSTRUCTIONS_AVAILABLE 19 |
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Paper <paper@tflc.us>
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403 #endif |
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|
404 /* All WinRT ARM devices are required to support NEON, but just in case. */ |
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Paper <paper@tflc.us>
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405 return IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE) != 0; |
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406 #elif (defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) || defined(__aarch64__) |
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407 return 1; /* ARMv8 always has non-optional NEON support. */ |
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Paper <paper@tflc.us>
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408 #elif defined(__VITA__) |
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409 return 1; |
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Paper <paper@tflc.us>
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410 #elif defined(__3DS__) |
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411 return 0; |
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Paper <paper@tflc.us>
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412 #elif defined(__APPLE__) && defined(__ARM_ARCH) && (__ARM_ARCH >= 7) |
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413 /* (note that sysctlbyname("hw.optional.neon") doesn't work!) */ |
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414 return 1; /* all Apple ARMv7 chips and later have NEON. */ |
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Paper <paper@tflc.us>
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415 #elif defined(__APPLE__) |
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Paper <paper@tflc.us>
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416 return 0; /* assume anything else from Apple doesn't have NEON. */ |
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Paper <paper@tflc.us>
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417 #elif !defined(__arm__) |
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418 return 0; /* not an ARM CPU at all. */ |
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Paper <paper@tflc.us>
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419 #elif defined(__OpenBSD__) |
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420 return 1; /* OpenBSD only supports ARMv7 CPUs that have NEON. */ |
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Paper <paper@tflc.us>
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421 #elif defined(HAVE_ELF_AUX_INFO) |
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Paper <paper@tflc.us>
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422 unsigned long hasneon = 0; |
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Paper <paper@tflc.us>
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423 if (elf_aux_info(AT_HWCAP, (void *)&hasneon, (int)sizeof(hasneon)) != 0) |
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Paper <paper@tflc.us>
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424 return 0; |
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Paper <paper@tflc.us>
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425 |
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Paper <paper@tflc.us>
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426 return ((hasneon & HWCAP_NEON) == HWCAP_NEON); |
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Paper <paper@tflc.us>
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427 #elif defined(__QNXNTO__) |
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Paper <paper@tflc.us>
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428 return SYSPAGE_ENTRY(cpuinfo)->flags & ARM_CPU_FLAG_NEON; |
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Paper <paper@tflc.us>
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429 #elif (defined(__linux__) || defined(__ANDROID__)) && defined(HAVE_GETAUXVAL) |
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430 return (getauxval(AT_HWCAP) & HWCAP_NEON) == HWCAP_NEON; |
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Paper <paper@tflc.us>
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diff
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|
431 #elif defined(__linux__) |
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Paper <paper@tflc.us>
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432 return readProcAuxvForNeon(); |
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Paper <paper@tflc.us>
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433 #elif defined(__ANDROID__) |
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Paper <paper@tflc.us>
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diff
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|
434 /* Use NDK cpufeatures to read either /proc/self/auxv or /proc/cpuinfo */ |
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Paper <paper@tflc.us>
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diff
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435 { |
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Paper <paper@tflc.us>
parents:
diff
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|
436 AndroidCpuFamily cpu_family = android_getCpuFamily(); |
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Paper <paper@tflc.us>
parents:
diff
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|
437 if (cpu_family == ANDROID_CPU_FAMILY_ARM) { |
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|
438 uint64_t cpu_features = android_getCpuFeatures(); |
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Paper <paper@tflc.us>
parents:
diff
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439 if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON) { |
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Paper <paper@tflc.us>
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440 return 1; |
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Paper <paper@tflc.us>
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|
441 } |
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Paper <paper@tflc.us>
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diff
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|
442 } |
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Paper <paper@tflc.us>
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443 return 0; |
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Paper <paper@tflc.us>
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diff
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|
444 } |
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Paper <paper@tflc.us>
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diff
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|
445 #elif defined(__RISCOS__) |
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Paper <paper@tflc.us>
parents:
diff
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446 /* Use the VFPSupport_Features SWI to access the MVFR registers */ |
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Paper <paper@tflc.us>
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|
447 { |
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Paper <paper@tflc.us>
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|
448 _kernel_swi_regs regs; |
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Paper <paper@tflc.us>
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449 regs.r[0] = 0; |
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Paper <paper@tflc.us>
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450 if (_kernel_swi(VFPSupport_Features, ®s, ®s) == NULL) { |
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parents:
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451 if ((regs.r[2] & 0xFFF000) == 0x111000) { |
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Paper <paper@tflc.us>
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diff
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|
452 return 1; |
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Paper <paper@tflc.us>
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diff
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|
453 } |
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Paper <paper@tflc.us>
parents:
diff
changeset
|
454 } |
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Paper <paper@tflc.us>
parents:
diff
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|
455 return 0; |
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Paper <paper@tflc.us>
parents:
diff
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|
456 } |
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Paper <paper@tflc.us>
parents:
diff
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|
457 #else |
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Paper <paper@tflc.us>
parents:
diff
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|
458 #warning vec_CPU_have_NEON is not implemented for this ARM platform. Write me. |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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diff
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|
459 return 0; |
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Paper <paper@tflc.us>
parents:
diff
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|
460 #endif |
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Paper <paper@tflc.us>
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diff
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|
461 } |
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Paper <paper@tflc.us>
parents:
diff
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|
462 |
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Paper <paper@tflc.us>
parents:
diff
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|
463 #define VEC_CPU_FEATURES_RESET VEC_UINT32_C(0xFFFFFFFF) |
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Paper <paper@tflc.us>
parents:
diff
changeset
|
464 |
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Paper <paper@tflc.us>
parents:
diff
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|
465 static vec_uint32 vec_CPU_features = VEC_CPU_FEATURES_RESET; |
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Paper <paper@tflc.us>
parents:
diff
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|
466 |
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Paper <paper@tflc.us>
parents:
diff
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|
467 vec_uint32 vec_get_CPU_features(void) |
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Paper <paper@tflc.us>
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diff
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|
468 { |
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Paper <paper@tflc.us>
parents:
diff
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|
469 if (vec_CPU_features == VEC_CPU_FEATURES_RESET) { |
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Paper <paper@tflc.us>
parents:
diff
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|
470 vec_CPU_get_CPUID_features(); |
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Paper <paper@tflc.us>
parents:
diff
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|
471 vec_CPU_features = 0; |
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Paper <paper@tflc.us>
parents:
diff
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|
472 if (vec_CPU_have_ALTIVEC()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
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|
473 vec_CPU_features |= VEC_CPU_HAS_ALTIVEC; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
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|
474 if (vec_CPU_have_ALTIVEC_VSX()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
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|
475 vec_CPU_features |= VEC_CPU_HAS_ALTIVEC_VSX; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
476 if (vec_CPU_have_MMX()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
477 vec_CPU_features |= VEC_CPU_HAS_MMX; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
478 if (vec_CPU_have_SSE()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
479 vec_CPU_features |= VEC_CPU_HAS_SSE; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
480 if (vec_CPU_have_SSE2()) |
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Paper <paper@tflc.us>
parents:
diff
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|
481 vec_CPU_features |= VEC_CPU_HAS_SSE2; |
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Paper <paper@tflc.us>
parents:
diff
changeset
|
482 if (vec_CPU_have_SSE3()) |
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Paper <paper@tflc.us>
parents:
diff
changeset
|
483 vec_CPU_features |= VEC_CPU_HAS_SSE3; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
484 if (vec_CPU_have_SSE41()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
485 vec_CPU_features |= VEC_CPU_HAS_SSE41; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
486 if (vec_CPU_have_SSE42()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
487 vec_CPU_features |= VEC_CPU_HAS_SSE42; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
488 if (vec_CPU_have_AVX()) |
e26874655738
*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
489 vec_CPU_features |= VEC_CPU_HAS_AVX; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
490 if (vec_CPU_have_AVX2()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
491 vec_CPU_features |= VEC_CPU_HAS_AVX2; |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
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|
492 if (vec_CPU_have_AVX512F()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
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|
493 vec_CPU_features |= VEC_CPU_HAS_AVX512F; |
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Paper <paper@tflc.us>
parents:
diff
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|
494 if (vec_CPU_have_NEON()) |
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*: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff
changeset
|
495 vec_CPU_features |= VEC_CPU_HAS_NEON; |
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Paper <paper@tflc.us>
parents:
diff
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|
496 } |
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Paper <paper@tflc.us>
parents:
diff
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|
497 return vec_CPU_features; |
25
92156fe32755
impl/ppc/altivec: update to new implementation
Paper <paper@tflc.us>
parents:
23
diff
changeset
|
498 } |