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comparison src/impl/x86/sse42.c @ 28:c6c99ab1088a

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*: add min/max functions and a big big refactor (again) agh, this time I added a few more implementations (and generally made the code just a little faster...)
author Paper <paper@tflc.us>
date Thu, 24 Apr 2025 00:54:02 -0400
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27:d00b95f95dd1 28:c6c99ab1088a
1 /**
2 * vec - a tiny SIMD vector library in C99
3 *
4 * Copyright (c) 2024 Paper
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 **/
24
25 #include "vec/impl/x86/sse42.h"
26 #include "vec/impl/generic.h"
27
28 #include <immintrin.h>
29
30 /* ------------------------------------------------------------------------ */
31 /* comparison */
32
33 #define MM_SET1_64(x) _mm_set1_epi64x(x)
34
35 /* helper funcs */
36 #define VEC_xSSE42_CMP(name, op, sign, bits, size, first, second, VARS, TRANS1, TRANS2) \
37 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse42_##name(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
38 { \
39 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
40 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
41 VARS \
42 \
43 TRANS1 \
44 \
45 vec1d->sse = _mm_##op##_epi##bits(vec##first##d->sse, vec##second##d->sse); \
46 \
47 TRANS2 \
48 \
49 return vec1d->vec; \
50 }
51
52 #define VEC_SSE42_CMP(name, op, bits, size, first, second) \
53 VEC_xSSE42_CMP(name, op, /* nothing */, bits, size, first, second, /* nothing */, /* nothing */, /* nothing */)
54
55 #define VEC_uSSE42_CMP(name, op, bits, size, first, second) \
56 VEC_xSSE42_CMP(name, op, u, bits, size, first, second, \
57 __m128i xor_val = MM_SET1_##bits(UINT64_C(1) << (bits - 1)); \
58 , { \
59 vec1d->sse = _mm_xor_si128(vec1d->sse, xor_val); \
60 vec2d->sse = _mm_xor_si128(vec2d->sse, xor_val); \
61 }, \
62 { \
63 /* nothing */ \
64 })
65
66 /* these are the same for unsigned and signed, for obvious reasons. */
67 #define VEC_SSE42_CMPEQ_64x2(sign) VEC_xSSE42_CMP(cmpeq, cmpeq, sign, 64, 2, 1, 2, , ,)
68
69 /* ------------------------------------------------------------------------ */
70
71 #define VEC_SSE42_CMPLT_64x2(sign) VEC_##sign##SSE42_CMP(cmplt, cmpgt, 64, 2, 2, 1)
72 #define VEC_SSE42_CMPGT_64x2(sign) VEC_##sign##SSE42_CMP(cmpgt, cmpgt, 64, 2, 1, 2)
73
74 #define VEC_SSE42_STRUCT_CMP_64x2(name, sign) v##sign##int64x2_sse42_##name
75
76 /* ------------------------------------------------------------------------ */
77
78 // SSE 4.1 provides a real _mm_mullo_epi32
79 #define VEC_SSE42_DEFINE_OPERATIONS_SIGN(sign, bits, size) \
80 union v##sign##int##bits##x##size##_impl_data { \
81 v##sign##int##bits##x##size vec; \
82 __m128i sse; \
83 }; \
84 \
85 VEC_STATIC_ASSERT(VEC_ALIGNOF(__m128i) <= VEC_ALIGNOF(v##sign##int##bits##x##size), "vec: v" #sign "int32x4 alignment needs to be expanded to fit intrinsic type size"); \
86 VEC_STATIC_ASSERT(sizeof(__m128i) <= sizeof(v##sign##int##bits##x##size), "vec: v" #sign "int32x4 needs to be expanded to fit intrinsic type size"); \
87 \
88 VEC_SSE42_CMPLT_##bits##x##size(sign); \
89 VEC_SSE42_CMPGT_##bits##x##size(sign); \
90 \
91 const v##sign##int##bits##x##size##_impl v##sign##int##bits##x##size##_impl_sse42 = { \
92 .cmplt = VEC_SSE42_STRUCT_CMP_##bits##x##size(cmplt, sign), \
93 .cmpgt = VEC_SSE42_STRUCT_CMP_##bits##x##size(cmpgt, sign), \
94 };
95
96 #define VEC_SSE42_DEFINE_OPERATIONS(bits, size) \
97 VEC_SSE42_DEFINE_OPERATIONS_SIGN(u, bits, size) \
98 VEC_SSE42_DEFINE_OPERATIONS_SIGN( , bits, size)
99
100 VEC_SSE42_DEFINE_OPERATIONS(64, 2)