# HG changeset patch
# User Paper <paper@tflc.us>
# Date 1732223951 0
# Node ID 627d548b23c839ce37be94bed57208a908e14354
# Parent  cf04071d2148ed0b647ab4f112495f68478443f1
impl/generic: fix load and store implementations

this caused a segmentation fault under AltiVec, but it went under
the radar on x86 because my main PC supports all of the non-generic
vector implementations.

diff -r cf04071d2148 -r 627d548b23c8 include/vec/impl/cpu.h
--- a/include/vec/impl/cpu.h	Wed Nov 20 14:33:19 2024 -0500
+++ b/include/vec/impl/cpu.h	Thu Nov 21 21:19:11 2024 +0000
@@ -311,8 +311,8 @@
 	void (*handler)(int sig);
 	handler = signal(SIGILL, vec_CPU_illegal_instruction);
 	if (!setjmp(vec_jmpbuf)) {
-		asm volatile("mtspr 256, %0\n\t"
-					 "vand %%v0, %%v0, %%v0" ::"r"(-1));
+		vector unsigned char vec;
+		vec_and(vec, vec);
 		altivec = 1;
 	}
 	signal(SIGILL, handler);
@@ -324,13 +324,14 @@
 {
 	volatile int vsx = 0;
 #if defined(VEC_COMPILER_HAS_ALTIVEC_VSX) && defined(__GNUC__)
+# warning Compiling UNTESTED code for VSX.
 	void (*handler)(int sig);
 	handler = signal(SIGILL, vec_CPU_illegal_instruction);
 	if (!setjmp(vec_jmpbuf)) {
 		// this is completely untested
-		asm volatile("mtspr 256, %0\n\t"
-					 "xxland %%v0, %%v0, %%v0" ::"r"(-1));
-		vsx = 1;
+		//__asm__ __volatile__("mtspr 256, %0\n\t"
+		//			 "xxland %%v0, %%v0, %%v0" ::"r"(-1));
+		//vsx = 1;
 	}
 	signal(SIGILL, handler);
 #endif
diff -r cf04071d2148 -r 627d548b23c8 include/vec/impl/generic.h
--- a/include/vec/impl/generic.h	Wed Nov 20 14:33:19 2024 -0500
+++ b/include/vec/impl/generic.h	Thu Nov 21 21:19:11 2024 +0000
@@ -78,18 +78,32 @@
 		return vec; \
 	} \
 	\
+	static v##sign##int##bits##x##size v##sign##int##bits##x##size##_generic_load(const vec_##sign##int##bits in[size]) \
+	{ \
+		v##sign##int##bits##x##size vec; \
+		vec.generic[0] = v##sign##int##bits##x##halfsize##_load(in); \
+		vec.generic[1] = v##sign##int##bits##x##halfsize##_load(in + halfsize); \
+		return vec; \
+	} \
+	\
 	static void v##sign##int##bits##x##size##_generic_store_aligned(v##sign##int##bits##x##size vec, vec_##sign##int##bits out[size]) \
 	{ \
 		v##sign##int##bits##x##halfsize##_store_aligned(vec.generic[0], out); \
 		v##sign##int##bits##x##halfsize##_store_aligned(vec.generic[1], out + halfsize); \
 	} \
 	\
+	static void v##sign##int##bits##x##size##_generic_store(v##sign##int##bits##x##size vec, vec_##sign##int##bits out[size]) \
+	{ \
+		v##sign##int##bits##x##halfsize##_store(vec.generic[0], out); \
+		v##sign##int##bits##x##halfsize##_store(vec.generic[1], out + halfsize); \
+	} \
+	\
 	static v##sign##int##bits##x##size##_impl v##sign##int##bits##x##size##_impl_generic = { \
 		/* .splat = */ NULL, \
 		v##sign##int##bits##x##size##_generic_load_aligned, \
-		v##sign##int##bits##x##size##_generic_load_aligned, \
+		v##sign##int##bits##x##size##_generic_load, \
 		v##sign##int##bits##x##size##_generic_store_aligned, \
-		v##sign##int##bits##x##size##_generic_store_aligned, \
+		v##sign##int##bits##x##size##_generic_store, \
 	};
 
 #define VEC_GENERIC_DEFINE_OPERATIONS(bits, size, halfsize) \
diff -r cf04071d2148 -r 627d548b23c8 include/vec/impl/ppc/altivec.h
--- a/include/vec/impl/ppc/altivec.h	Wed Nov 20 14:33:19 2024 -0500
+++ b/include/vec/impl/ppc/altivec.h	Thu Nov 21 21:19:11 2024 +0000
@@ -178,6 +178,11 @@
 		v##sign##int##bits##x##size##_altivec_lshift, \
 		v##sign##int##bits##x##size##_altivec_rshift, \
 		VEC_ALTIVEC_STRUCT_##sign##LRSHIFT(sign, csign, bits, size), \
+		/* .cmplt = */ NULL, \
+		/* .cmple = */ NULL, \
+		/* .cmpeq = */ NULL, \
+		/* .cmpgt = */ NULL, \
+		/* .cmpge = */ NULL, \
 	};
 
 #define VEC_DEFINE_OPERATIONS(bits, size) \
diff -r cf04071d2148 -r 627d548b23c8 test/test_compare.h
--- a/test/test_compare.h	Wed Nov 20 14:33:19 2024 -0500
+++ b/test/test_compare.h	Thu Nov 21 21:19:11 2024 +0000
@@ -109,4 +109,4 @@
 #undef RUN_TESTS
 
 	return ret;
-}
\ No newline at end of file
+}