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annotate src/impl/x86/sse2.c @ 23:e26874655738

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*: huge refactor, new major release (hahaha) I keep finding things that are broken... The problem NOW was that vec would unintentionally build some functions with extended instruction sets, which is Bad and would mean that for all intents and purposes the CPU detection was completely broken. Now vec is no longer header only either. Boohoo. However this gives a lot more flexibility to vec since we no longer want or need to care about C++ crap. The NEON and Altivec implementations have not been updated which means they won't compile hence why they're commented out in the cmake build file.
author Paper <paper@tflc.us>
date Sun, 24 Nov 2024 02:52:40 -0500
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children e49e70f7012f
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23
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1 /**
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2 * vec - a tiny SIMD vector library in C99
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3 *
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4 * Copyright (c) 2024 Paper
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5 *
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 * of this software and associated documentation files (the "Software"), to deal
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8 * in the Software without restriction, including without limitation the rights
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 * copies of the Software, and to permit persons to whom the Software is
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11 * furnished to do so, subject to the following conditions:
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12 *
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13 * The above copyright notice and this permission notice shall be included in all
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14 * copies or substantial portions of the Software.
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15 *
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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22 * SOFTWARE.
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23 **/
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24
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25 #include "vec/impl/x86/sse2.h"
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26 #include "vec/impl/generic.h"
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27
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28 #include <emmintrin.h>
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29
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30 #define VEC_SSE2_OPERATION_8x16(op, sign) \
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31 do { \
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32 /* unpack and multiply */ \
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33 union v##sign##int8x16_impl_data *vec1d = (union v##sign##int8x16_impl_data *)&vec1; \
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34 union v##sign##int8x16_impl_data *vec2d = (union v##sign##int8x16_impl_data *)&vec2; \
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35 \
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36 __m128i dst_even = _mm_##op##_epi16(vec1d->sse, vec2d->sse); \
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37 __m128i dst_odd = _mm_##op##_epi16(_mm_srli_epi16(vec1d->sse, 8), _mm_srli_epi16(vec2d->sse, 8)); \
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38 \
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39 /* repack */ \
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40 vec1d->sse = _mm_or_si128( \
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41 _mm_slli_epi16(dst_odd, 8), \
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42 _mm_srli_epi16(_mm_slli_epi16(dst_even, 8), 8) \
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43 ); \
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44 return vec1d->vec; \
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45 } while (0)
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46
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47 // shared between SSE2 variations
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48 #define VEC_SSE2_MUL_8x16(sign) \
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49 VEC_SSE2_OPERATION_8x16(mullo, sign)
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50
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51 #define VEC_SSE2_MUL_16x8(sign) \
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52 do { \
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53 /* we have a real instruction for this */ \
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54 union v##sign##int16x8_impl_data *vec1d = (union v##sign##int16x8_impl_data *)&vec1; \
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55 union v##sign##int16x8_impl_data *vec2d = (union v##sign##int16x8_impl_data *)&vec2; \
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56 \
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57 vec1d->sse = _mm_mullo_epi16(vec1d->sse, vec2d->sse); \
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58 return vec1d->vec; \
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59 } while (0)
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60
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61 #define VEC_SSE2_MUL_32x4(sign) \
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62 do { \
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63 /* this was stolen from... somewhere :) */ \
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64 union v##sign##int32x4_impl_data *vec1d = (union v##sign##int32x4_impl_data *)&vec1; \
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65 union v##sign##int32x4_impl_data *vec2d = (union v##sign##int32x4_impl_data *)&vec2; \
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66 \
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67 __m128i a13 = _mm_shuffle_epi32(vec1d->sse, 0xF5); /* (-,a3,-,a1) */ \
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68 __m128i b13 = _mm_shuffle_epi32(vec2d->sse, 0xF5); /* (-,b3,-,b1) */ \
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69 __m128i prod02 = _mm_mul_epu32(vec1d->sse, vec2d->sse); /* (-,a2*b2,-,a0*b0) */ \
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70 __m128i prod13 = _mm_mul_epu32(a13, b13); /* (-,a3*b3,-,a1*b1) */ \
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71 __m128i prod01 = _mm_unpacklo_epi32(prod02,prod13); /* (-,-,a1*b1,a0*b0) */ \
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72 __m128i prod23 = _mm_unpackhi_epi32(prod02,prod13); /* (-,-,a3*b3,a2*b2) */ \
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73 \
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74 vec1d->sse = _mm_srl_epi64(prod01, prod23); /* (ab3,ab2,ab1,ab0) */ \
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75 return vec1d->vec; \
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76 } while (0)
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77
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78 #define VEC_SSE2_MUL_64x2(sign) \
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79 do { \
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80 union v##sign##int64x2_impl_data *vec1d = (union v##sign##int64x2_impl_data *)&vec1; \
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81 union v##sign##int64x2_impl_data *vec2d = (union v##sign##int64x2_impl_data *)&vec2; \
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82 \
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83 __m128i ac = _mm_mul_epu32(vec1d->sse, vec2d->sse); /* ac = (vec1 & UINT32_MAX) * (vec2 & UINT32_MAX); */ \
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84 __m128i b = _mm_srli_epi64(vec1d->sse, 32); /* b = vec1 >> 32; */ \
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85 __m128i bc = _mm_mul_epu32(b, vec2d->sse); /* bc = b * (vec2 & UINT32_MAX); */ \
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86 __m128i d = _mm_srli_epi64(vec2d->sse, 32); /* d = vec2 >> 32; */ \
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87 __m128i ad = _mm_mul_epu32(vec1d->sse, d); /* ad = (vec1 & UINT32_MAX) * d; */ \
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88 __m128i hi = _mm_add_epi64(bc, ad); /* hi = bc + ad; */ \
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89 hi = _mm_slli_epi64(hi, 32); /* hi <<= 32; */ \
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90 \
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91 vec1d->sse = _mm_add_epi64(hi, ac); /* (ab3,ab2,ab1,ab0) */ \
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92 return vec1d->vec; \
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93 } while (0)
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94
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95 #define VEC_SSE2_CMPEQ_8x16(sign) \
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96 do { \
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97 union v##sign##int8x16_impl_data *vec1d = (union v##sign##int8x16_impl_data *)&vec1; \
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98 union v##sign##int8x16_impl_data *vec2d = (union v##sign##int8x16_impl_data *)&vec2; \
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99 \
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100 vec1d->sse = _mm_cmpeq_epi8(vec1d->sse, vec2d->sse); \
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101 return vec1d->vec; \
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102 } while (0)
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103
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104 #define VEC_SSE2_CMPEQ_16x8(sign) \
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105 do { \
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106 union v##sign##int16x8_impl_data *vec1d = (union v##sign##int16x8_impl_data *)&vec1; \
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107 union v##sign##int16x8_impl_data *vec2d = (union v##sign##int16x8_impl_data *)&vec2; \
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108 \
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109 vec1d->sse = _mm_cmpeq_epi16(vec1d->sse, vec2d->sse); \
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110 return vec1d->vec; \
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111 } while (0)
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112
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113 #define VEC_SSE2_CMPEQ_32x4(sign) \
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114 do { \
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115 union v##sign##int32x4_impl_data *vec1d = (union v##sign##int32x4_impl_data *)&vec1; \
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116 union v##sign##int32x4_impl_data *vec2d = (union v##sign##int32x4_impl_data *)&vec2; \
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117 \
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118 vec1d->sse = _mm_cmpeq_epi32(vec1d->sse, vec2d->sse); \
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119 return vec1d->vec; \
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120 } while (0)
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121
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122 // SSE2 doesn't have an intrinsic for 64x2 equality comparison,
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123 // so how can we take a 32x4 comparison result and turn it into
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124 // a 64x2 comparison result?
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125 //
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126 // well, Intel conveniently provided an operation where we can
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127 // shuffle around 32-bit integers (_mm_shuffle_epi32).
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128 //
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129 // this means all we have to do is simply do the 32-bit operation,
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130 // shuffle the parts, and then return a bitwise AND of the result.
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131
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132 #define VEC_SSE2_CMPEQ_64x2(sign) \
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133 do { \
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Paper <paper@tflc.us>
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134 union v##sign##int64x2_impl_data *vec1d = (union v##sign##int64x2_impl_data *)&vec1; \
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135 union v##sign##int64x2_impl_data *vec2d = (union v##sign##int64x2_impl_data *)&vec2; \
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Paper <paper@tflc.us>
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136 \
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Paper <paper@tflc.us>
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diff changeset
137 vec1d->sse = _mm_cmpeq_epi32(vec1d->sse, vec2d->sse); \
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Paper <paper@tflc.us>
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138 vec2d->sse = _mm_shuffle_epi32(vec1d->sse, _MM_SHUFFLE(1, 1, 3, 3)); \
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139 vec1d->sse = _mm_shuffle_epi32(vec1d->sse, _MM_SHUFFLE(0, 0, 2, 2)); \
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140 vec1d->sse = _mm_and_si128(vec1d->sse, vec2d->sse); \
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141 \
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Paper <paper@tflc.us>
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142 return vec1d->vec; \
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Paper <paper@tflc.us>
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143 } while (0)
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144
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145 #define VEC_SSE2_DEFINE_OPERATIONS_SIGN(sign, bits, size) \
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146 union v##sign##int##bits##x##size##_impl_data { \
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147 v##sign##int##bits##x##size vec; \
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148 __m128i sse; \
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149 }; \
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150 \
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151 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_load_aligned(const vec_##sign##int##bits in[size]) \
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152 { \
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153 union v##sign##int##bits##x##size##_impl_data vec; \
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154 vec.sse = _mm_load_si128((const __m128i *)in); \
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155 return vec.vec; \
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156 } \
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157 \
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158 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_load(const vec_##sign##int##bits in[size]) \
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159 { \
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Paper <paper@tflc.us>
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160 union v##sign##int##bits##x##size##_impl_data vec; \
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161 vec.sse = _mm_loadu_si128((const __m128i *)in); \
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162 return vec.vec; \
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163 } \
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Paper <paper@tflc.us>
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164 \
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165 void v##sign##int##bits##x##size##_sse2_store_aligned(v##sign##int##bits##x##size vec, vec_##sign##int##bits out[size]) \
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166 { \
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Paper <paper@tflc.us>
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167 _mm_store_si128((__m128i *)out, ((union v##sign##int##bits##x##size##_impl_data *)&vec)->sse); \
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168 } \
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Paper <paper@tflc.us>
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169 \
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170 void v##sign##int##bits##x##size##_sse2_store(v##sign##int##bits##x##size vec, vec_##sign##int##bits out[size]) \
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171 { \
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172 _mm_storeu_si128((__m128i *)out, ((union v##sign##int##bits##x##size##_impl_data *)&vec)->sse); \
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173 } \
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Paper <paper@tflc.us>
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174 \
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Paper <paper@tflc.us>
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175 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_add(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
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Paper <paper@tflc.us>
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176 { \
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Paper <paper@tflc.us>
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177 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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178 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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179 \
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Paper <paper@tflc.us>
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180 vec1d->sse = _mm_add_epi##bits(vec1d->sse, vec2d->sse); \
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181 return vec1d->vec; \
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Paper <paper@tflc.us>
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182 } \
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Paper <paper@tflc.us>
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183 \
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Paper <paper@tflc.us>
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184 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_sub(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
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185 { \
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Paper <paper@tflc.us>
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186 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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187 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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188 \
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Paper <paper@tflc.us>
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189 vec1d->sse = _mm_sub_epi##bits(vec1d->sse, vec2d->sse); \
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Paper <paper@tflc.us>
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190 return vec1d->vec; \
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Paper <paper@tflc.us>
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191 } \
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Paper <paper@tflc.us>
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192 \
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Paper <paper@tflc.us>
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193 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_mul(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
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Paper <paper@tflc.us>
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194 { \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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195 VEC_SSE2_MUL_##bits##x##size(sign); \
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Paper <paper@tflc.us>
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196 } \
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Paper <paper@tflc.us>
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197 \
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Paper <paper@tflc.us>
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198 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_and(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
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Paper <paper@tflc.us>
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199 { \
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Paper <paper@tflc.us>
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200 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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Paper <paper@tflc.us>
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201 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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202 \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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diff changeset
203 vec1d->sse = _mm_and_si128(vec1d->sse, vec2d->sse); \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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204 return vec1d->vec; \
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Paper <paper@tflc.us>
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diff changeset
205 } \
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Paper <paper@tflc.us>
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206 \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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207 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_or(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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diff changeset
208 { \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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209 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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Paper <paper@tflc.us>
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210 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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Paper <paper@tflc.us>
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211 \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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diff changeset
212 vec1d->sse = _mm_or_si128(vec1d->sse, vec2d->sse); \
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Paper <paper@tflc.us>
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213 return vec1d->vec; \
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Paper <paper@tflc.us>
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diff changeset
214 } \
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Paper <paper@tflc.us>
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215 \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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216 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_xor(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
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Paper <paper@tflc.us>
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diff changeset
217 { \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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218 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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219 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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Paper <paper@tflc.us>
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220 \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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221 vec1d->sse = _mm_xor_si128(vec1d->sse, vec2d->sse); \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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222 return vec1d->vec; \
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Paper <paper@tflc.us>
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223 } \
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Paper <paper@tflc.us>
parents:
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224 \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
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225 v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_cmpeq(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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diff changeset
226 { \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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227 VEC_SSE2_CMPEQ_##bits##x##size(sign); \
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Paper <paper@tflc.us>
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diff changeset
228 } \
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Paper <paper@tflc.us>
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229 \
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Paper <paper@tflc.us>
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230 const v##sign##int##bits##x##size##_impl v##sign##int##bits##x##size##_impl_sse2 = { \
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Paper <paper@tflc.us>
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231 v##sign##int##bits##x##size##_generic_splat, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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diff changeset
232 v##sign##int##bits##x##size##_sse2_load_aligned, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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233 v##sign##int##bits##x##size##_sse2_load, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
234 v##sign##int##bits##x##size##_sse2_store_aligned, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
235 v##sign##int##bits##x##size##_sse2_store, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
236 v##sign##int##bits##x##size##_sse2_add, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
237 v##sign##int##bits##x##size##_sse2_sub, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
238 v##sign##int##bits##x##size##_sse2_mul, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
239 v##sign##int##bits##x##size##_generic_div, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
240 v##sign##int##bits##x##size##_generic_avg, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
241 v##sign##int##bits##x##size##_sse2_and, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
242 v##sign##int##bits##x##size##_sse2_or, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
243 v##sign##int##bits##x##size##_sse2_xor, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
244 v##sign##int##bits##x##size##_generic_not, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
245 v##sign##int##bits##x##size##_generic_lshift, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
246 v##sign##int##bits##x##size##_generic_rshift, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
247 v##sign##int##bits##x##size##_generic_lrshift, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
248 v##sign##int##bits##x##size##_generic_cmplt, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
249 v##sign##int##bits##x##size##_generic_cmple, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
250 v##sign##int##bits##x##size##_sse2_cmpeq, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
251 v##sign##int##bits##x##size##_generic_cmpge, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
parents:
diff changeset
252 v##sign##int##bits##x##size##_generic_cmpgt, \
e26874655738 *: huge refactor, new major release (hahaha)
Paper <paper@tflc.us>
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253 };
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254
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255 #define VEC_SSE2_DEFINE_OPERATIONS(bits, size) \
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256 VEC_SSE2_DEFINE_OPERATIONS_SIGN(u, bits, size) \
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257 VEC_SSE2_DEFINE_OPERATIONS_SIGN( , bits, size)
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258
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259 // SSE is *only* 128-bit
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260 VEC_SSE2_DEFINE_OPERATIONS(8, 16)
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261 VEC_SSE2_DEFINE_OPERATIONS(16, 8)
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262 VEC_SSE2_DEFINE_OPERATIONS(32, 4)
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263 VEC_SSE2_DEFINE_OPERATIONS(64, 2)