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annotate src/impl/x86/sse2.c @ 28:c6c99ab1088a

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*: add min/max functions and a big big refactor (again) agh, this time I added a few more implementations (and generally made the code just a little faster...)
author Paper <paper@tflc.us>
date Thu, 24 Apr 2025 00:54:02 -0400
parents e49e70f7012f
children bf6ad516f1e6
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e26874655738 *: huge refactor, new major release (hahaha)
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1 /**
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2 * vec - a tiny SIMD vector library in C99
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3 *
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4 * Copyright (c) 2024 Paper
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5 *
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 * of this software and associated documentation files (the "Software"), to deal
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8 * in the Software without restriction, including without limitation the rights
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 * copies of the Software, and to permit persons to whom the Software is
e26874655738 *: huge refactor, new major release (hahaha)
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11 * furnished to do so, subject to the following conditions:
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12 *
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13 * The above copyright notice and this permission notice shall be included in all
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14 * copies or substantial portions of the Software.
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15 *
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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22 * SOFTWARE.
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23 **/
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24
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25 #include "vec/impl/x86/sse2.h"
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26
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27 #include <emmintrin.h>
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28
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29 #define VEC_SSE2_DEFINE_IMPL_DATA(sign, bits, size) \
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30 union v##sign##int##bits##x##size##_impl_data { \
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31 v##sign##int##bits##x##size vec; \
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32 __m128i sse; \
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33 }; \
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34 \
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35 VEC_STATIC_ASSERT(VEC_ALIGNOF(__m128i) <= VEC_ALIGNOF(v##sign##int##bits##x##size), "vec: v" #sign "int" #bits "x" #size " alignment needs to be expanded to fit intrinsic type size"); \
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36 VEC_STATIC_ASSERT(sizeof(__m128i) <= sizeof(v##sign##int##bits##x##size), "vec: v" #sign "int" #bits "x" #size " needs to be expanded to fit intrinsic type size");
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37
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38 VEC_SSE2_DEFINE_IMPL_DATA( , 8, 16)
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39 VEC_SSE2_DEFINE_IMPL_DATA(u, 8, 16)
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40 VEC_SSE2_DEFINE_IMPL_DATA( , 16, 8)
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41 VEC_SSE2_DEFINE_IMPL_DATA(u, 16, 8)
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42 VEC_SSE2_DEFINE_IMPL_DATA( , 32, 4)
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43 VEC_SSE2_DEFINE_IMPL_DATA(u, 32, 4)
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44 VEC_SSE2_DEFINE_IMPL_DATA( , 64, 2)
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45 VEC_SSE2_DEFINE_IMPL_DATA(u, 64, 2)
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46
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47 /* eh */
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48 #define MM_SET1_8(x) _mm_set1_epi8(x)
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49 #define MM_SET1_16(x) _mm_set1_epi16(x)
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50 #define MM_SET1_32(x) _mm_set1_epi32(x)
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51 #define MM_SET1_64(x) _mm_set1_epi64x(x)
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52
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53 /* ------------------------------------------------------------------------ */
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54
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55 /* unfortunately doing this for SSE2 is PREPROCESSOR HELL */
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56 #define VEC_SSE2_MINMAX_8x16_TEMPLATE(SIGN, OP, VALS, ADDITIONAL1, ADDITIONAL2) \
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57 VEC_FUNC_IMPL v##SIGN##int8x16 v##SIGN##int8x16_sse2_##OP(v##SIGN##int8x16 vec1, v##SIGN##int8x16 vec2) \
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58 { \
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59 union v##SIGN##int8x16_impl_data *vec1d = (union v##SIGN##int8x16_impl_data *)&vec1; \
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60 union v##SIGN##int8x16_impl_data *vec2d = (union v##SIGN##int8x16_impl_data *)&vec2; \
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61 VALS \
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62 \
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63 ADDITIONAL1 \
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64 \
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65 vec1d->sse = _mm_##OP##_epu8(vec1d->sse, vec2d->sse); \
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66 \
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67 ADDITIONAL2 \
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68 \
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69 return vec1d->vec; \
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70 }
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71
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72 /* conveniently, this looks like K&R C ;) */
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73 #define VEC_SSE2_MINMAX_8x16(OP) \
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74 VEC_SSE2_MINMAX_8x16_TEMPLATE(/* nothing */, OP, \
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75 __m128i xor_val = _mm_set1_epi8(0x80u); \
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76 , { \
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77 vec1d->sse = _mm_xor_si128(vec1d->sse, xor_val); \
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78 vec2d->sse = _mm_xor_si128(vec2d->sse, xor_val); \
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79 }, \
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80 { \
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81 vec1d->sse = _mm_xor_si128(vec1d->sse, xor_val); \
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82 })
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83
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84 #define VEC_SSE2_MINMAX_u8x16(OP) \
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85 VEC_SSE2_MINMAX_8x16_TEMPLATE(u, OP, /* nothing */, /* nothing */, /* nothing */)
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86
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87 #define VEC_SSE2_MINMAX_16x8_TEMPLATE(SIGN, OP, VALS, ADDITIONAL1, ADDITIONAL2) \
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88 VEC_FUNC_IMPL v##SIGN##int16x8 v##SIGN##int16x8_sse2_##OP(v##SIGN##int16x8 vec1, v##SIGN##int16x8 vec2) \
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89 { \
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90 union v##SIGN##int16x8_impl_data *vec1d = (union v##SIGN##int16x8_impl_data *)&vec1; \
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91 union v##SIGN##int16x8_impl_data *vec2d = (union v##SIGN##int16x8_impl_data *)&vec2; \
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92 VALS \
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93 \
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94 ADDITIONAL1 \
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95 \
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96 vec1d->sse = _mm_##OP##_epi16(vec1d->sse, vec2d->sse); \
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97 \
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98 ADDITIONAL2 \
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99 \
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100 return vec1d->vec; \
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101 }
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102
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103 #define VEC_SSE2_MINMAX_16x8(OP) \
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104 VEC_SSE2_MINMAX_16x8_TEMPLATE(/* nothing */, OP, /* nothing */, /* nothing */, /* nothing */)
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105
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106 #define VEC_SSE2_MINMAX_u16x8(OP) \
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107 VEC_SSE2_MINMAX_16x8_TEMPLATE(u, OP, \
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108 __m128i xor_val = _mm_set1_epi16(0x8000u); \
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109 , { \
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110 vec1d->sse = _mm_xor_si128(vec1d->sse, xor_val); \
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111 vec2d->sse = _mm_xor_si128(vec2d->sse, xor_val); \
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112 }, \
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113 { \
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114 vec1d->sse = _mm_xor_si128(vec1d->sse, xor_val); \
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115 })
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116
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117 #define VEC_SSE2_MINMAX_32x4(OP) /* none */
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118 #define VEC_SSE2_MINMAX_64x2(OP) /* none */
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119 #define VEC_SSE2_MINMAX_u32x4(OP) /* none */
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120 #define VEC_SSE2_MINMAX_u64x2(OP) /* none */
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121
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122 #define VEC_SSE2_STRUCT_MINMAX_8x16(OP, SIGN) v##SIGN##int8x16_sse2_##OP
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123 #define VEC_SSE2_STRUCT_MINMAX_16x8(OP, SIGN) v##SIGN##int16x8_sse2_##OP
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124 #define VEC_SSE2_STRUCT_MINMAX_32x4(OP, SIGN) NULL
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125 #define VEC_SSE2_STRUCT_MINMAX_64x2(OP, SIGN) NULL
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126
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127 /* ------------------------------------------------------------------------ */
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128 /* multiplication */
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129
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130 #define VEC_SSE2_OPERATION_8x16(op, sign) \
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131 do { \
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132 /* unpack and multiply */ \
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133 union v##sign##int8x16_impl_data *vec1d = (union v##sign##int8x16_impl_data *)&vec1; \
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134 union v##sign##int8x16_impl_data *vec2d = (union v##sign##int8x16_impl_data *)&vec2; \
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135 \
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136 __m128i dst_even = _mm_##op##_epi16(vec1d->sse, vec2d->sse); \
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137 __m128i dst_odd = _mm_##op##_epi16(_mm_srli_epi16(vec1d->sse, 8), _mm_srli_epi16(vec2d->sse, 8)); \
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138 \
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139 /* repack */ \
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140 vec1d->sse = _mm_or_si128( \
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141 _mm_slli_epi16(dst_odd, 8), \
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142 _mm_srli_epi16(_mm_slli_epi16(dst_even, 8), 8) \
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143 ); \
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144 return vec1d->vec; \
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145 } while (0)
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146
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147 // shared between SSE2 variations
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148 #define VEC_SSE2_MUL_8x16(sign) \
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149 VEC_SSE2_OPERATION_8x16(mullo, sign)
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150
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151 #define VEC_SSE2_MUL_16x8(sign) \
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152 do { \
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153 /* we have a real instruction for this */ \
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154 union v##sign##int16x8_impl_data *vec1d = (union v##sign##int16x8_impl_data *)&vec1; \
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155 union v##sign##int16x8_impl_data *vec2d = (union v##sign##int16x8_impl_data *)&vec2; \
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156 \
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157 vec1d->sse = _mm_mullo_epi16(vec1d->sse, vec2d->sse); \
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158 return vec1d->vec; \
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159 } while (0)
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160
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161 #define VEC_SSE2_MUL_32x4(sign) \
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162 do { \
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163 /* this was stolen from... somewhere :) */ \
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164 union v##sign##int32x4_impl_data *vec1d = (union v##sign##int32x4_impl_data *)&vec1; \
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165 union v##sign##int32x4_impl_data *vec2d = (union v##sign##int32x4_impl_data *)&vec2; \
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166 \
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167 __m128i a13 = _mm_shuffle_epi32(vec1d->sse, 0xF5); /* (-,a3,-,a1) */ \
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168 __m128i b13 = _mm_shuffle_epi32(vec2d->sse, 0xF5); /* (-,b3,-,b1) */ \
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169 __m128i prod02 = _mm_mul_epu32(vec1d->sse, vec2d->sse); /* (-,a2*b2,-,a0*b0) */ \
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170 __m128i prod13 = _mm_mul_epu32(a13, b13); /* (-,a3*b3,-,a1*b1) */ \
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171 __m128i prod01 = _mm_unpacklo_epi32(prod02,prod13); /* (-,-,a1*b1,a0*b0) */ \
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172 __m128i prod23 = _mm_unpackhi_epi32(prod02,prod13); /* (-,-,a3*b3,a2*b2) */ \
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173 \
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174 vec1d->sse = _mm_srl_epi64(prod01, prod23); /* (ab3,ab2,ab1,ab0) */ \
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175 return vec1d->vec; \
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176 } while (0)
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177
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178 #define VEC_SSE2_MUL_64x2(sign) \
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179 do { \
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180 union v##sign##int64x2_impl_data *vec1d = (union v##sign##int64x2_impl_data *)&vec1; \
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181 union v##sign##int64x2_impl_data *vec2d = (union v##sign##int64x2_impl_data *)&vec2; \
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182 \
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183 __m128i ac = _mm_mul_epu32(vec1d->sse, vec2d->sse); /* ac = (vec1 & UINT32_MAX) * (vec2 & UINT32_MAX); */ \
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184 __m128i b = _mm_srli_epi64(vec1d->sse, 32); /* b = vec1 >> 32; */ \
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185 __m128i bc = _mm_mul_epu32(b, vec2d->sse); /* bc = b * (vec2 & UINT32_MAX); */ \
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186 __m128i d = _mm_srli_epi64(vec2d->sse, 32); /* d = vec2 >> 32; */ \
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187 __m128i ad = _mm_mul_epu32(vec1d->sse, d); /* ad = (vec1 & UINT32_MAX) * d; */ \
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188 __m128i hi = _mm_add_epi64(bc, ad); /* hi = bc + ad; */ \
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189 hi = _mm_slli_epi64(hi, 32); /* hi <<= 32; */ \
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190 \
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191 vec1d->sse = _mm_add_epi64(hi, ac); /* (ab3,ab2,ab1,ab0) */ \
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192 return vec1d->vec; \
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193 } while (0)
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194
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195 /* ------------------------------------------------------------------------ */
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196 /* comparison */
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197
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198 /* helper funcs */
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199 #define VEC_xSSE2_CMP(name, op, sign, bits, size, first, second, VARS, TRANS1, TRANS2) \
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200 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_##name(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
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201 { \
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202 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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203 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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204 VARS \
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205 \
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206 TRANS1 \
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207 \
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208 vec1d->sse = _mm_##op##_epi##bits(vec##first##d->sse, vec##second##d->sse); \
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209 \
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210 TRANS2 \
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211 \
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212 return vec1d->vec; \
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213 }
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214
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215 #define VEC_SSE2_CMP(name, op, bits, size, first, second) \
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216 VEC_xSSE2_CMP(name, op, /* nothing */, bits, size, first, second, /* nothing */, /* nothing */, /* nothing */)
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217
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218 #define VEC_uSSE2_CMP(name, op, bits, size, first, second) \
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219 VEC_xSSE2_CMP(name, op, u, bits, size, first, second, \
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220 __m128i xor_val = MM_SET1_##bits(1u << (bits - 1)); \
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221 , { \
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222 vec1d->sse = _mm_xor_si128(vec1d->sse, xor_val); \
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223 vec2d->sse = _mm_xor_si128(vec2d->sse, xor_val); \
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224 }, \
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225 { \
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226 /* nothing */ \
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227 })
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228
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229 /* these are the same for unsigned and signed, for obvious reasons. */
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230 #define VEC_SSE2_CMPEQ_8x16(sign) VEC_xSSE2_CMP(cmpeq, cmpeq, sign, 8, 16, 1, 2, , ,)
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231 #define VEC_SSE2_CMPEQ_16x8(sign) VEC_xSSE2_CMP(cmpeq, cmpeq, sign, 16, 8, 1, 2, , ,)
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232 #define VEC_SSE2_CMPEQ_32x4(sign) VEC_xSSE2_CMP(cmpeq, cmpeq, sign, 32, 4, 1, 2, , ,)
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233
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234 /* SSE2 doesn't have an intrinsic for 64x2 equality comparison,
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235 * so how can we take a 32x4 comparison result and turn it into
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236 * a 64x2 comparison result?
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237 *
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238 * well, Intel conveniently provided an operation where we can
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239 * shuffle around 32-bit integers (_mm_shuffle_epi32).
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240 *
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241 * this means all we have to do is simply do the 32-bit operation,
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242 * shuffle the parts, and then return a bitwise AND of the result. */
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243
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244 #define VEC_SSE2_CMPEQ_64x2(sign) \
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245 VEC_FUNC_IMPL v##sign##int64x2 v##sign##int64x2_sse2_cmpeq(v##sign##int64x2 vec1, v##sign##int64x2 vec2) \
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246 { \
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247 union v##sign##int64x2_impl_data *vec1d = (union v##sign##int64x2_impl_data *)&vec1; \
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248 union v##sign##int64x2_impl_data *vec2d = (union v##sign##int64x2_impl_data *)&vec2; \
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249 \
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250 vec1d->sse = _mm_cmpeq_epi32(vec1d->sse, vec2d->sse); \
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251 vec2d->sse = _mm_shuffle_epi32(vec1d->sse, _MM_SHUFFLE(1, 1, 3, 3)); \
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252 vec1d->sse = _mm_shuffle_epi32(vec1d->sse, _MM_SHUFFLE(0, 0, 2, 2)); \
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253 vec1d->sse = _mm_and_si128(vec1d->sse, vec2d->sse); \
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254 \
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255 return vec1d->vec; \
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256 }
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257
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258 /* ------------------------------------------------------------------------ */
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259
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diff changeset
260 #define VEC_SSE2_CMPLT_8x16(sign) VEC_##sign##SSE2_CMP(cmplt, cmpgt, 8, 16, 2, 1)
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261 #define VEC_SSE2_CMPLT_16x8(sign) VEC_##sign##SSE2_CMP(cmplt, cmpgt, 16, 8, 2, 1)
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262 #define VEC_SSE2_CMPLT_32x4(sign) VEC_##sign##SSE2_CMP(cmplt, cmpgt, 32, 4, 2, 1)
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263 #define VEC_SSE2_CMPLT_64x2(sign) /* nothing */
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264
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diff changeset
265 #define VEC_SSE2_CMPGT_8x16(sign) VEC_##sign##SSE2_CMP(cmpgt, cmpgt, 8, 16, 1, 2)
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266 #define VEC_SSE2_CMPGT_16x8(sign) VEC_##sign##SSE2_CMP(cmpgt, cmpgt, 16, 8, 1, 2)
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267 #define VEC_SSE2_CMPGT_32x4(sign) VEC_##sign##SSE2_CMP(cmpgt, cmpgt, 32, 4, 1, 2)
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268 #define VEC_SSE2_CMPGT_64x2(sign) /* nothing */
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269
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270 #define VEC_SSE2_STRUCT_CMP_8x16(name, sign) v##sign##int8x16_sse2_##name
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271 #define VEC_SSE2_STRUCT_CMP_16x8(name, sign) v##sign##int16x8_sse2_##name
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272 #define VEC_SSE2_STRUCT_CMP_32x4(name, sign) v##sign##int32x4_sse2_##name
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273 #define VEC_SSE2_STRUCT_CMP_64x2(name, sign) NULL
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274
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275 /* ------------------------------------------------------------------------ */
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276
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277 #define VEC_SSE2_DEFINE_OPERATIONS_SIGN(sign, bits, size) \
28
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278 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_splat(vec_##sign##int##bits x) \
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279 { \
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280 union v##sign##int##bits##x##size##_impl_data vec; \
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diff changeset
281 vec.sse = MM_SET1_##bits(x); \
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282 return vec.vec; \
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diff changeset
283 } \
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284 \
28
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285 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_load_aligned(const vec_##sign##int##bits in[size]) \
23
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286 { \
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287 union v##sign##int##bits##x##size##_impl_data vec; \
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288 vec.sse = _mm_load_si128((const __m128i *)in); \
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289 return vec.vec; \
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290 } \
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291 \
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292 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_load(const vec_##sign##int##bits in[size]) \
23
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293 { \
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294 union v##sign##int##bits##x##size##_impl_data vec; \
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295 vec.sse = _mm_loadu_si128((const __m128i *)in); \
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296 return vec.vec; \
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297 } \
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298 \
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299 VEC_FUNC_IMPL void v##sign##int##bits##x##size##_sse2_store_aligned(v##sign##int##bits##x##size vec, vec_##sign##int##bits out[size]) \
23
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300 { \
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301 _mm_store_si128((__m128i *)out, ((union v##sign##int##bits##x##size##_impl_data *)&vec)->sse); \
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302 } \
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Paper <paper@tflc.us>
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303 \
28
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diff changeset
304 VEC_FUNC_IMPL void v##sign##int##bits##x##size##_sse2_store(v##sign##int##bits##x##size vec, vec_##sign##int##bits out[size]) \
23
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305 { \
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diff changeset
306 _mm_storeu_si128((__m128i *)out, ((union v##sign##int##bits##x##size##_impl_data *)&vec)->sse); \
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307 } \
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Paper <paper@tflc.us>
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diff changeset
308 \
28
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diff changeset
309 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_add(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
23
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310 { \
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Paper <paper@tflc.us>
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311 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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312 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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313 \
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Paper <paper@tflc.us>
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314 vec1d->sse = _mm_add_epi##bits(vec1d->sse, vec2d->sse); \
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315 return vec1d->vec; \
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Paper <paper@tflc.us>
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316 } \
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Paper <paper@tflc.us>
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diff changeset
317 \
28
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diff changeset
318 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_sub(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
23
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319 { \
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Paper <paper@tflc.us>
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320 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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321 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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Paper <paper@tflc.us>
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322 \
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Paper <paper@tflc.us>
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323 vec1d->sse = _mm_sub_epi##bits(vec1d->sse, vec2d->sse); \
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324 return vec1d->vec; \
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Paper <paper@tflc.us>
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325 } \
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Paper <paper@tflc.us>
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diff changeset
326 \
28
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Paper <paper@tflc.us>
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diff changeset
327 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_mul(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
23
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Paper <paper@tflc.us>
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328 { \
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Paper <paper@tflc.us>
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329 VEC_SSE2_MUL_##bits##x##size(sign); \
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diff changeset
330 } \
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Paper <paper@tflc.us>
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331 \
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diff changeset
332 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_and(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
23
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Paper <paper@tflc.us>
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diff changeset
333 { \
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Paper <paper@tflc.us>
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334 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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diff changeset
335 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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Paper <paper@tflc.us>
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336 \
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Paper <paper@tflc.us>
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337 vec1d->sse = _mm_and_si128(vec1d->sse, vec2d->sse); \
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diff changeset
338 return vec1d->vec; \
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Paper <paper@tflc.us>
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339 } \
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Paper <paper@tflc.us>
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340 \
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diff changeset
341 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_or(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
23
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Paper <paper@tflc.us>
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342 { \
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Paper <paper@tflc.us>
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343 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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344 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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345 \
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Paper <paper@tflc.us>
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346 vec1d->sse = _mm_or_si128(vec1d->sse, vec2d->sse); \
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347 return vec1d->vec; \
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348 } \
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Paper <paper@tflc.us>
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349 \
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diff changeset
350 VEC_FUNC_IMPL v##sign##int##bits##x##size v##sign##int##bits##x##size##_sse2_xor(v##sign##int##bits##x##size vec1, v##sign##int##bits##x##size vec2) \
23
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Paper <paper@tflc.us>
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351 { \
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Paper <paper@tflc.us>
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352 union v##sign##int##bits##x##size##_impl_data *vec1d = (union v##sign##int##bits##x##size##_impl_data *)&vec1; \
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353 union v##sign##int##bits##x##size##_impl_data *vec2d = (union v##sign##int##bits##x##size##_impl_data *)&vec2; \
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354 \
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Paper <paper@tflc.us>
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355 vec1d->sse = _mm_xor_si128(vec1d->sse, vec2d->sse); \
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Paper <paper@tflc.us>
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356 return vec1d->vec; \
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Paper <paper@tflc.us>
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diff changeset
357 } \
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Paper <paper@tflc.us>
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diff changeset
358 \
28
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diff changeset
359 VEC_SSE2_CMPEQ_##bits##x##size(sign); \
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diff changeset
360 VEC_SSE2_CMPLT_##bits##x##size(sign); \
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diff changeset
361 VEC_SSE2_CMPGT_##bits##x##size(sign); \
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Paper <paper@tflc.us>
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diff changeset
362 \
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Paper <paper@tflc.us>
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diff changeset
363 VEC_SSE2_MINMAX_##sign##bits##x##size(min) \
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Paper <paper@tflc.us>
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diff changeset
364 VEC_SSE2_MINMAX_##sign##bits##x##size(max) \
23
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Paper <paper@tflc.us>
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365 \
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366 const v##sign##int##bits##x##size##_impl v##sign##int##bits##x##size##_impl_sse2 = { \
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367 .splat = v##sign##int##bits##x##size##_sse2_splat, \
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368 .load_aligned = v##sign##int##bits##x##size##_sse2_load_aligned, \
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369 .load = v##sign##int##bits##x##size##_sse2_load, \
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370 .store_aligned = v##sign##int##bits##x##size##_sse2_store_aligned, \
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371 .store = v##sign##int##bits##x##size##_sse2_store, \
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372 .add = v##sign##int##bits##x##size##_sse2_add, \
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373 .sub = v##sign##int##bits##x##size##_sse2_sub, \
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374 .mul = v##sign##int##bits##x##size##_sse2_mul, \
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375 .band = v##sign##int##bits##x##size##_sse2_and, \
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376 .bor = v##sign##int##bits##x##size##_sse2_or, \
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377 .bxor = v##sign##int##bits##x##size##_sse2_xor, \
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378 .cmpeq = v##sign##int##bits##x##size##_sse2_cmpeq, \
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379 .cmplt = VEC_SSE2_STRUCT_CMP_##bits##x##size(cmplt, sign), \
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380 .cmpgt = VEC_SSE2_STRUCT_CMP_##bits##x##size(cmpgt, sign), \
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381 .min = VEC_SSE2_STRUCT_MINMAX_##bits##x##size(min, sign), \
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382 .max = VEC_SSE2_STRUCT_MINMAX_##bits##x##size(max, sign), \
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383 };
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384
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385 #define VEC_SSE2_DEFINE_OPERATIONS(bits, size) \
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386 VEC_SSE2_DEFINE_OPERATIONS_SIGN(u, bits, size) \
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387 VEC_SSE2_DEFINE_OPERATIONS_SIGN( , bits, size)
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388
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389 // SSE is *only* 128-bit
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390 VEC_SSE2_DEFINE_OPERATIONS(8, 16)
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391 VEC_SSE2_DEFINE_OPERATIONS(16, 8)
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392 VEC_SSE2_DEFINE_OPERATIONS(32, 4)
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393 VEC_SSE2_DEFINE_OPERATIONS(64, 2)